The background and embodiments of the invention will be described with reference to a SONOS memory cell, but it will be understood that the invention is not limited thereto.
A typical SONOS layer stack of a SONOS memory cell contains the following layer sequence (from top to bottom):                a polysilicon layer;        a top blocking oxide layer;        a silicon oxynitride layer;        a bottom (or tunnel) oxide layer; and        a silicon layer (substrate).        
The top blocking oxide may for example be formed with, or by, a silicon dioxide (SiO2) layer. The bottom oxide layer may be formed in a similar manner. The bottom silicon layer is typically formed by the substrate, which, in a typical MOSFET type transistor, would contain a channel region between source and drain terminals. Layer thicknesses, impurity content or material variations in the SONOS layer stack are well known to a person skilled in the art. Some non-limiting examples will be given below in the description of embodiments of the invention.
The present inventor has appreciated that the thickness of the top blocking oxide layer of a SONOS memory cell may vary from batch to batch in a typical prior art manufacturing process due to the exposure of the top blocking oxide layer to chemicals such as hot phosphoric acid used to remove a sacrificial capping nitride on top of the top blocking oxide layer. During removal of this sacrificial capping nitride layer by hot phosphoric acid, the top blocking oxide will also be (partly) etched away. The inventor has appreciated that the amount of top blocking oxide loss may be highly influenced by the age of the acid in the etching tank and the number of times the acid in the tank has been used in such processes.
The variation in top blocking oxide thickness from batch to batch may be up to about 20 Å or more when comparing the use of a fresh etchant chemical to the use of an aged etchant chemical in the etching tank. In particular, the variation of top blocking oxide thickness can cause a significant variation in the programming windows of the SONOS cell. It may also result in early reliability failures and yield loss. Thus batch-to-batch thickness variation of the top blocking oxide layer is highly undesirable.
In order to help with the understanding of the present invention we will now describe a typical prior art process in more detail. In this typical prior art process, a SONOS memory cell bottom oxide with a thickness range from about 16 Å to about 20 Å (1 Å=10−10 m) and silicon oxynitride with a thickness range from about 100 Å to about 150 Å is formed in a single step in a LPCVD furnace. After the bottom oxide and silicon oxynitride is formed, a top blocking oxide with a thickness range from about 20 Å to about 60 Å is formed by a high temperature LPCVD oxidation furnace or wet oxidation based process by converting some of the silicon oxynitride to top oxide so as to form a top blocking oxide layer on the remaining silicon oxynitride. Subsequently, a capping nitride layer with a thickness range from about 200 Å to about 400 Å is deposited by LPCVD furnace on top of the top blocking oxide. The capping nitride is used as a hard mask in an integration process. Next, an ONO (oxide-nitride-oxide) photoresist mask is used to pattern the device area where the SONOS cell will be defined and where other “non-SONOS” (also referred to as “periphery” in the subsequent text and drawings) areas are to be removed. With the ONO mask, the capping nitride layer will be etched by a highly isotropic dry etching process in the non-SONOS device area until the top blocking oxide is exposed. Next, the ONO mask is stripped. At this stage, the non-SONOS area has an exposed top blocking oxide while the capping nitride layer remains in the SONOS device area. Hydrofluoric (HF) dipping is carried out to remove the top blocking oxide in the non-SONOS device area so as to expose the oxynitride layer, while in the SONOS device area the capping nitride layer remains as a protecting hard mask during HF dipping for the ONO layer located underneath. In the next step, hot phosphoric acid dipping is used to completely remove the silicon oxynitride layer in the non-SONOS device area, while a portion of similar thickness of the capping nitride layer will also be removed in the SONOS device area. After this step, in the SONOS device area, the remaining capping nitride layer with a thickness range from about 100 Å to about 150 Å continues to serve as a hard mask to protect the ONO layer located underneath. In the non-SONOS device area, the silicon oxynitride layer is completely removed so as to expose an implant buffer oxide layer. The next step is the implantation process for the logic devices in the non-SONOS device area (the SONOS device area is masked so that the logic devices will be formed outside the SONOS device area). After the implantation and removal of the photoresist, the implant buffer oxide layer is removed by a HF dipping process so as to expose the bare silicon surface to prepare for the subsequent gate oxidation process. The remaining sacrificial capping nitride layer on top of the ONO device area will be removed by hot phosphoric acid in the next step, which finally exposes the top blocking oxide layer in the SONOS device area. During removal of this capping nitride using hot phosphoric acid, the top blocking oxide will be partially removed and the amount (or thickness) that is removed is highly uncontrollable. The amount removed will be influenced by the age of the hot phosphoric acid and the number of process cycles which the hot phosphoric acid in the tank has previously been subjected to, as described earlier. The thickness of the top blocking oxide removed due to the hot phosphoric acid may vary from 0 Å to about 20 Å depending on the type of top blocking oxide used in the SONOS memory cell. Thus the individual film layer thicknesses of the ONO layers (which at this point in the process have been finally determined) may vary from batch to batch. The process then continues with subsequent gate oxidation processes which together constitute a triple gate oxidation process. This triple gate oxidation forms the gate oxides for the High Voltage (HV), Medium Voltage (MV) and Low Voltage (LV) devices in the non-SONOS device area. The first gate oxidation step in this triple gate oxidation results in an oxidation with a thickness range from about 80 Å to about 90 Å on the entire wafer. This is followed by the application of a photoresist mask to pattern the HV region. Using this HV mask, the oxidation in the MV/LV region will be removed by a HF wet etch. After photoresist removal and cleans, a second gate oxidation with a thickness range from about 70 Å to about 80 Å is then performed in a furnace dry oxidation tool. This is followed by application of a photoresist mask to mask the HV/MV region, and etching of the LV region by a HF wet etch. After photoresist removal and cleans, a third gate oxidation with in situ steam generation gate oxidation (ISSG) is then grown in a rapid thermal oxidation tool for the LV (low voltage) device with a thickness range from about 20 Å to about 35 Å in silicon. During the triple gate oxidation process, the SONOS device area will be exposed to a marginal increase of oxide on top of the original top blocking oxide (20-60 Å), resulting in a final top blocking oxide thickness of approximately 25-65 Å. Finally, in the HV region the gate oxide will be approximately 120-130 Å, in the MV region it will be 70-80 Å and in the LV region it will be 20-30 Å. Finally, gate polysilicon with a thickness range from about 1500 Å to about 2500 Å is deposited as the gate electrode for the SONOS device and periphery devices.